1. Field of the Invention
The present invention relates to a plasma display apparatus. More particularly, the present invention relates to a plasma display apparatus and a driving method thereof in which an erroneous discharge or abnormal discharge is prevented, a darkroom contrast is increased, an operation margin is widened, and an influence of a lower substrate wall charge is reduced in a sustain discharge.
2. Discussion of the Related Art
A plasma display apparatus displays a picture by exciting a phosphor using an ultraviolet ray, which is generated when an inert mixture gas such as He+Xe, Ne+Xe, or He+Ne+Xe is discharged. In the plasma display apparatus, thinning and large-scaling are not only facilitated, but also picture quality is improved due to a recent technology development.
In FIG. 1, in order to display a grayscale image, the plasma display apparatus is driven by dividing one frame into several sub-fields each having a different number of light emission times. Each of the sub-fields is divided to have a reset period for initializing a whole image, an address period for selecting a scan line and selecting a discharge cell at the selected scan line, and a sustain period for embodying a grayscale based on the number of discharge times. For example, when an image is displayed in 256 grayscales, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight sub-fields (SF1 to SF8). As described above, each of the eight sub-fields (SF1 to SF8) is divided into the reset period, the address period and the sustain period. The reset period and the address period are identical at each sub-field, whereas the sustain period and the number of sustain pulses allocated are increased in a ratio of 2n (where n=0,1,2,3,4,5,6,7) for each sub-field.
FIG. 2 is a schematic plan view illustrating an electrode arrangement of a related art three-electrode alternate current surface discharge type plasma display panel (Hereinafter, referred to as “PDP”).
In FIG. 2, the alternate current surface discharge type PDP includes scan electrodes (Y1 to Yn) and sustain electrodes (Z) formed on an upper substrate; and address electrodes (X1 to Xm) formed on a lower substrate and right-angled with the scan electrodes (Y1 to Yn) and the sustain electrodes (Z).
Discharge cells 1 are arranged in matrix form at an intersection of the scan electrodes (Y1 to Yn), the sustain electrodes (Z) and the address electrodes (X1 to Xm) to express any one of red, green and blue.
A dielectric layer and an MgO protective layer are layered on the upper substrate having the scan electrodes (Y1 to Yn) and the sustain electrodes (Z).
A barrier rib is formed on the lower substrate having the address electrodes (X1 to Xm) to prevent optic and electric confusion between adjacent discharge cells 1. Phosphor is formed on the lower substrate and the barrier rib and excited by an ultraviolet ray, thereby emitting a visible ray.
An inert mixture gas such as He+Xe, Ne+Xe and He+Xe+Ne is injected into a discharge space provided between the upper substrate and the lower substrate in the PDP.
FIG. 3 illustrates a driving wave form applied to the PDP of FIG. 2. The driving wave form of FIG. 3 is described with reference to wall charge distributions of FIGS. 4A to 4E.
In FIG. 3, each of sub-fields (SFn−1, SFn) includes a reset period (RP) for initializing the discharge cells 1 of a whole image, an address period (AP) for selecting the discharge cell, a sustain period (SP) for sustaining the discharge of the selected discharge cell 1, and an erasure period (EP) for erasing wall charges in the discharge cell 1.
In the erasure period (EP) of the (n−1)th sub-field (SFn−1), an erasure ramp wave form (ERR) is applied to sustain electrodes (Z). During the erasure period (EP), Ovolts is applied to the scan electrodes (Y) and the address electrodes (X). The erasure ramp wave form (ERR) is a positive ramp wave form gradually rising from Ovolts to a positive ramp wave form (Vs). By the erasure ramp wave form (ERR), an erasure discharge is generated between the scan electrode (Y) and the sustain electrode (Z) in on-cells where a sustain discharge is generated. As a result, each of the discharge cells 1 has the wall charge distribution of FIG. 4A soon after the erasure period (EP).
In a set-up period (SU) of the reset period (RP) at which the nth sub-field (SFn) begins, a positive ramp wave form (PR) is applied to all the scan electrodes (Y), and 0V is applied to the sustain electrodes (Z) and the address electrodes (X). By the positive ramp wave form (PR) of the set-up period (SU), a voltage of the scan electrode (Y) gradually rises from the positive sustain voltage (Vs) to a reset voltage (Vr) higher than the positive sustain voltage (Vs). By the positive ramp wave form (PR), a dark discharge not almost generating light is generated between the scan electrodes (Y) and the address electrodes (X) and is concurrently generated between the scan electrodes (Y) and the sustain electrodes (Z) in the discharge cells of the whole image. As a result of the dark discharge, soon after the set-up period (SU), as shown in FIG. 4B, positive wall charges remain on the address electrodes (X) and the sustain electrodes (Z), and negative wall charges remain on the scan electrodes (Y). While the dark discharge is generated at the set-up period (SU), gap voltages (Vg) between the scan electrodes (Y) and the sustain electrodes (Z) and between the scan electrodes (Y) and the address electrodes (X) are initialized closely to a firing voltage (Vf) causing the discharge.
In a set-down period (SD) of the reset period (RP) subsequent to the set-up period (SU), a negative ramp wave form (NR) is applied to the scan electrodes (Y). At the same time, a positive sustain voltage (Vs) is applied to the sustain electrodes (Z), and 0V is applied to the address electrodes (X). By the negative ramp wave form (NR), the voltage of the scan electrode (Y) drops from the positive sustain voltage (Vs) to a negative erasure voltage (Ve). By the negative ramp wave form (NR), the dark discharge is generated between the scan electrodes (Y) and the address electrodes (X) and is concurrently generated between the scan electrodes (Y) and the sustain electrodes (Z) in the whole discharge cells of the whole image. As a result of the dark discharge of the set-down period (SD), the wall charge distribution of each of the discharge cells 1 is changed to be in an optimal address condition as shown in FIG. 4C. In this time, excessive wall charges that are unnecessary for an address discharge are erased from the scan electrodes (Y) and the address electrodes (X), and a predetermined amount of wall charges remain in each of the discharge cells 1. As the negative wall charges are shifted from the scan electrodes (Y) and accumulated on the sustain electrodes (Z), the polarity of positive wall charges of the sustain electrodes (Z) are negatively inverted. While the dark discharge is generated in the set-down period (SD) of the reset period (RP), gap voltages between the scan electrodes (Y) and the sustain electrodes (Z) and between the scan electrodes (Y) and the address electrodes (X) are close to the firing voltage (Vf).
In the address period (AP), a negative scan pulse (−SCNP) is sequentially applied to the scan electrodes (Y) and at the same time, a positive data pulse (DP) is applied to the address electrodes (X) in synchronization with the negative scan pulse (−SCNP). A voltage of the scan pulse (−SCNP) is a scan voltage (Vsc) falling from 0V or a negative scan bias voltage (Vyb) close thereto to a negative scan voltage (−Vy). A voltage of the data pulse (DP) is a positive data voltage (Va). During the address period (AP), a positive Z bias voltage (Vzb) lower than the positive sustain voltage (Vs) is supplied to the sustain electrodes (Z). While the gap voltage between the scan electrodes (Y) and the address electrodes (X) exceeds the firing voltage (Vf) in a state where the gap voltage is adjusted closely to the firing voltage (Vf) soon after the reset period (RP), the address discharge is generated between the electrodes (Y, X) in the on-cells having the scan voltage (Vsc) and the data voltage (Va) applied thereto. A primary address discharge, which is generated between the scan electrodes (Y) and the address electrodes (X), generates charged particles in the discharge cell to induce a secondary discharge between the scan electrodes (Y) and the sustain electrodes (Z) as shown in FIG. 4D. FIG. 4E illustrates the wall charge distribution in the on-cells where the address discharge is generated.
The wall charge distribution of off-cells where the address discharge is not generated is substantially sustained to a state of FIG. 4C.
In the sustain period (SP), sustain pulses (SUSP) of the positive sustain voltage (Vs) is alternately applied to the scan electrodes (Y) and the sustain electrodes (Z). By doing so, the on-cells selected by the address discharge generates the sustain discharge between the scan electrodes (Y) and the sustain electrodes (Z) at each of the sustain pulses (SUSP) owing to the wall charge distribution of FIG. 4E. In contrast, the off-cells do not generate the discharge during the sustain period. This is because the wall charge distribution of the off-cells is sustained in a state of FIG. 4C and therefore, when the positive sustain voltage (Vs) is applied to the scan electrodes (Y), the gap voltage between the scan electrodes (Y) and the sustain electrodes (Z) cannot exceed the firing voltage (Vf).
However, the related art plasma display apparatus has a drawback in that during the erasure period (EP) of the (n−1)th sub-field (SFn−1) and the reset period (RP) of the nth sub-field (SFn), the discharge cells 1 are initialized and a number of discharge times is performed for controlling the wall charge, thereby reducing a darkroom contrast value and accordingly reducing a contrast ratio. In Table 1, arranged are discharge types and the number of discharge times performed in the erasure period (EP) and the reset period (RP) of the previous sub-field (SFn−1) in the related art plasma display apparatus.
TABLE 1Oper. periodCell stateRP of SFnEP ofSFn-1SUSDOn-cell turned on atOpposite dischargeX◯◯SFn-1(Y-X)Surface discharge◯◯◯(Y-Z)Off-cell turned off atOpposite dischargeX◯◯SFn-1(Y-X)Surface dischargeX◯◯(Y-Z)
As shown in Table 1, when the on-cells are turned on at the (n−1)th sub-field (SFn−1), during the erasure period (EP) and the reset period (RP), three times of surface discharge are performed between the scan electrodes (Y) and the sustain electrodes (Z) and two times of opposite discharge are generated between the scan electrodes (Y) and the address electrodes (X). When the off-cells are turned off in the previous sub-field (SFn), during the erasure period (EP) and the reset period (RP), two times of surface discharge are performed between the scan electrodes (Y) and the sustain electrodes (Z), and two times of opposite discharge are generated between the scan electrodes (Y) and the address electrodes (X).
The number of discharge times performed in the erasure period and the reset period causes an increase in an amount of light emission in the erasure period and the reset period, thereby reducing the darkroom contrast value. In consideration of a contrast characteristic, the amount of light emission should be minimized if possible. Specifically, since the surface discharge generates a great amount of light emission in comparison to the opposite discharge, the surface discharge has a great bad influence upon darkroom contrast in comparison to the opposite discharge.
In the related art plasma display apparatus, the negative wall charges are excessively accumulated on the scan electrodes (Y) since the wall charges are not well erased in the erasure period (EP) of the (n−1)th sub-field (SFn−1). Therefore, the dark discharge is not generated in the setup period (SU) of the nth sub-field (SFn). If the dark discharge is not normally performed in the setup period (SU), the discharge cells are not initialized. Accordingly, the reset voltage (Vr) should be increased in order to generate the discharge in the setup period. If the dark discharge is not performed in the setup period (SU), the discharge cell is not in an optimal address condition soon after the reset period. Therefore, an abnormal discharge or an erroneous discharge is caused. In a case where the positive wall charges are excessively accumulated on the scan electrodes (Y) soon after the erasure period (EP) of the (n−1)th sub-field (SFn−1), a strong discharge is generated, thereby not uniformly initializing the whole discharge cells when the positive sustain voltage (Vs) being an initiation voltage of a positive ramp wave form (PR) is applied to the scan electrodes (Y) in the setup period (SU) of the nth sub-field (SFn). The above drawbacks will be in detail described with reference to FIG. 5.
FIG. 5 illustrates an external voltage (Vyz) applied between the scan electrodes (Y) and the sustain electrodes (Z) and the gap voltage (Vg) in the discharge cell in the setup period (SU). Here, the external applied voltage (Vyz) is illustrated using a solid line in FIG. 5, and is applied to each of the scan electrodes (Y) and the sustain electrodes (Z). Since 0V is applied to the sustain electrodes (Z), the external applied voltage (Vyz) is substantially identical with the positive ramp wave form (PR). In FIG. 5, dotted lines {circle around (1)}, {circle around (2)} and {circle around (3)} indicate the gap voltages (Vg) formed in the discharge gas by the wall charges of the discharge cell. The gap voltages (Vg) are different as shown in the dotted lines {circle around (1)}, {circle around (2)} and {circle around (3)} because the wall charges are different in amount in the discharge cell depending on whether or not the discharge is generated in the previous sub-field. The external voltage (Vyz) is applied between the scan electrodes (Y) and the sustain electrodes (Z). The gap voltage (Vg) is formed in the discharge gas of the discharge cell.
A relation of the external voltage (Vyz) and the gap voltage (Vg) is expressed in the following Equation 1:Vyz=Vg+Vw  [Equation 1]
In FIG. 5, “{circle around (1)}” denotes the gap voltage (Vg) where the wall charges are sufficiently erased and minimized in the discharge cell. If the gap voltage (Vg) is increased in proportion to the external applied voltage (Vyz) and reaches the firing voltage (Vf), the dark discharge is generated. By the dark discharge, the gap voltage is initialized to the firing voltage (Vf) in the discharge cells.
In FIG. 5, “{circle around (2)}” denotes the gap voltage (Vg) where the strong discharge is generated during the erasure period (EP) of the (n−1)th sub-field (SFn−1) to invert polarities of the wall charges in the wall charge distribution of the discharge cells. Soon after the erasure period (EP), the negative wall charges accumulated on the scan electrodes (Y) are positively inverted in polarity due to the strong discharge. This is caused by the discharge cell having a low uniformity or by the erasure ramp wave form (ERR) varied in slope depending on a temperature variation in a large-scaled plasma display panel. In this time, the initial gap voltage (Vg) is excessively increased as shown in FIG. 5, and therefore, the positive sustain voltage (Vs) is applied to the scan electrodes (Y) in the setup period (SU) and at the same time, the gap voltage (Vg) exceeds the firing voltage (Vf), thereby generating the strong discharge. By the strong discharge, the discharge cells are not initialized to have the wall charge distribution of the optimal address condition, that is, to have the wall charge distribution of FIG. 4C in the setup period (SU) and the setdown period (SD) and therefore, the address discharge can be generated in the off-cells that should be turned off. In other words, when the erasure discharge is strongly generated in the erasure period prior to the reset period, the erroneous discharge can be generated.
In FIG. 5, “{circle around (3)}” denotes the gap voltage (Vg) where during the erasure period (EP) of the (n−1)th sub-field (SFn−1), the erasure discharge is not generated or is very weakly generated to maintain without variation the wall charge distribution in the discharge cells. The wall charge distribution is formed as a result of the sustain discharge performed just before the erasure discharge.
In a detailed description, as shown in FIG. 3, the last sustain discharge is generated when the sustain pulse (SUSP) is applied to the scan electrodes (Y). As a result of the last sustain discharge, the negative wall charges remain on the scan electrodes (Y) and the positive wall charges remain on the sustain electrodes (Z). The wall charges should be erased for a normal initialization at a next sub-field, but if the erasure discharge is not performed or is very weakly performed, their polarities are sustained without change. The erasure discharge is not performed or is very weakly performed because the discharge cell has a low uniformity or the erasure ramp wave form (ERR) is varied in slope due to the temperature variance in the PDP. Since the initial gap voltage (Vg) is a very low negative voltage as shown in FIG. 5, the reference {circle around (3)}, the gap voltage (Vg) of the discharge cells does not reach the firing voltage (Vf) even though the positive ramp wave form (RP) rises to the reset voltage (Vr) in the setup period. Therefore, the dark discharge is not generated in the setup period (SU) and the setdown period (SD). As a result, when the erasure discharge is not generated or is very weakly generated in the erasure period before the reset period, an erroneous discharge or an abnormal discharge is caused due to the abnormal initialization.
In FIG. 5 reference {circle around (3)}, a relation of the gap voltage (Vg) and the firing voltage (Vf) is expressed in the following Equation 2, and in FIG. 5 reference {circle around (3)}, a relation of the gap voltage (Vg) and the firing voltage (Vf) is expressed in the following Equation 3:Vgini+Vs>Vf  [Equation 2]Vgini+Vr<Vf  [Equation 3]                where Vgini: initial gap voltage just before the setup period (SU) begins, as shown in FIG. 5.        
A gap voltage condition (or a wall charge condition) for allowing the normal initialization in the erasure period (EP) and the reset period (RP) in consideration of the above drawback is expressed in the following Equation 4 satisfying all the Equations 2 and 3:Vf−Vr<Vgini<Vf−Vs  [Equation 4]
As a result, if the initial gap voltage (Vgini) does not satisfy Equation 4 before the setup period (SU), the related art plasma display apparatus can cause an erroneous discharge, a misdischarge or an abnormal discharge, and a narrow operation margin. In other words, in the related art plasma display apparatus, an erasure operation should be normally performed in order to secure an operation reliability and margin, but it may be abnormally performed depending on a discharge cell uniformity or a use temperature in the PDP.
The related art plasma display apparatus has a drawback in that the wall charge distribution gets unstable due to excessive spatial charges and their active momentum in a high-temperature environment, thereby causing the erroneous discharge, the misdischarge or the abnormal discharge and accordingly, the narrow operation margin. This will be described in detail with reference to FIGS. 6A to 6C.
In the high-temperature environment, an amount and a momentum of the spatial charges 61 are generated in the discharge in comparison to a room-temperature environment or a low-temperature environment. Accordingly, the spatial charges 61 are generated in the sustain discharge of the (n−1)th sub-field (SFn−1), and are in active motion in the discharge space even after the setup period (SU) of the nth sub-field (SFn) as shown in FIG. 6A.
In a state where the spatial charges 61 having large momentums exist in the discharge space as shown in FIG. 6A, a data voltage (Va) is applied to the address electrode (X) and a scan voltage (−Vy) is applied to the scan electrode (SU) during the address period. If so, as a result of the setup discharge of the setup period (SU), the positive spatial charges 61 are recombined with the negative wall charges accumulated on the scan electrode (Y) and the negative spatial charges 61 are recombined with the positive wall charges accumulated on the address electrode (Y), as shown in FIG. 6B.
As a result, the negative wall charges formed by the setup discharge are erased from the scan electrode (Y) and the positive wall charges formed by the setup discharge are erased from the address electrode (X) as shown in FIG. 6C. Accordingly, even though the data voltage (Va) and the scan voltage (−Vy) are applied to the address electrode (X) and the scan electrode (Y), the gap voltage (Vg) does not reach the firing voltage (Vf). Therefore, the address discharge is not generated. Accordingly, there is a drawback in that on-cells are often miswritten if the driving wave form of FIG. 3 is applied to the PDP in the high-temperature environment.
In the related art plasma display apparatus, if a nonuniformity of a lower substrate structure (for example, a shape nonuniformity of a barrier rib or a thickness nonuniformity of phosphor) is caused by a process error, the wall charges accumulated on the lower substrate between adjacent discharge cells can be greatly different in amount. In a data modulation using a data pattern where any one of adjacent discharge cells functions as the on-cell and the other functions as the off-cell to generate the discharge only at one-side on-cell, or using a dither mask having the same effect, the wall charges accumulated on the lower substrate between the adjacent discharge cells can be greatly different in amount. If the wall charges accumulated on the lower substrate of the adjacent discharge cells are different in amount and the wall charges are excessively accumulated on the lower substrate of an undesired off-cell among them, the off-cell is erroneously discharged during the sustain period and displayed as a spot. This erroneous spot discharge is caused by a great influence of the wall charges of the lower substrate upon the sustain discharge, and is generally caused in the plasma display apparatus having a great nonuniformity at an edge of the lower substrate due to the process error.
FIG. 7 is an enlarged view illustrating a driving wave form, which is applied to each of the electrodes (X, Y and Z) between the address period (AP) and the sustain period (SP). FIG. 8 is a view illustrating a first sustain discharge mechanism generated by a first sustain pulse (FSTSUSP).
Referring to FIGS. 7 and 8, if 0V is applied to the address electrode (X) and the sustain electrode (Z) and a voltage of the scan electrode (Y) is varied from 0V to the sustain voltage (Vs) by the first sustain pulse (FSTSUSP), the first sustain discharge is generated in a corresponding discharge cell. However, if the negative wall charges are much accumulated on the lower substrate of the discharge cell, the discharge is generated between the scan electrode (Y) and the sustain electrode (Z) and at the same time, the discharge is strongly generated between the scan electrode (Y) and the address electrode (X). As mentioned above, the sustain discharge is influenced by the wall charges accumulated on the lower substrate and therefore, a green-colored or magenta-colored spot is generated with a low grayscale near a corner of the PDP.